In a semiconductor device of a reverse-blocking type, a reverse-blocking capability equivalent to a forward-blocking capability is required. For securing the reverse-blocking capability, it is necessary to make a p-n junction holding a reverse breakdown voltage to extend from the bottom surface of a semiconductor chip to its top surface. A diffused layer for forming the p-n junction extending from the bottom surface to the top surface is an isolation layer.
FIG. 10 illustrates the manufacturing steps of forming an isolation layer in a related reverse-blocking IGBT presenting its principal part. The method is that of forming the isolation layer by coating and diffusion. First, on a semiconductor wafer 1, an oxide film 2 having a film thickness of the order of 2.5 μm is formed by thermal oxidation as a dopant diffusion mask (step (a)). Next, the oxide film 2 is subjected to patterning and etching, by which an opening 3 with a diameter of the order of 100 μm is formed for forming an isolation layer (step (b)). Thereafter, the opening 3 is coated with a boron source 4 and high temperature and long time heat treatment of the semiconductor wafer 1 is carried out in a diffusion furnace to form a p-type diffused layer with a thickness of the order of several hundreds micrometers (step (c)). The p-type diffused layer becomes the isolation layer 5.
Thereafter, although not particularly illustrated, after a top surface structure is formed, the semiconductor wafer 1 is made thinner by grinding its bottom surface until the bottom surface 6 reaches the isolation layer 5. On the ground bottom surface 6, a bottom surface structure made up of a p+ collector region and a collector electrode is formed. Subsequently, the semiconductor wafer 1 is cut at a scribing line positioned at the center of the isolation layer 5 to form an IGBT chip.
FIG. 11 is a cross-sectional view showing the principal part of the related reverse-blocking IGBT whose isolation layer 5 is formed according to the manufacturing steps shown in FIG. 10. Reference numeral 8 denotes a p+ well region, 10 denotes a p voltage withstanding region, 9 denotes a gate insulator film, 12 denotes a field oxide film, 7 denotes a p+ collector region and 11 denotes a dicing face. Illustration of an emitter region selectively formed on the surface in the p well region 8, a gate electrode on the gate insulator film 9, an interlayer insulator film further covering the gate electrode, an emitter electrode on the interlayer insulator film, a field plate formed on the field oxide film 12, and a collector electrode covering the collector region 7 are not illustrated.
The isolation layer is formed in another way in a related reverse-blocking IGBT by providing a trench and forming a diffusion layer on the side wall of the trench as shown in FIGS. 12A-12C. Here, on a semiconductor wafer 14, an etching mask is first formed with a thick oxide film 13 having a thickness of several micrometers (FIG. 12A). Next, a trench 15 having a depth of the order of several hundreds micrometers is formed by dry etching (FIG. 12B). Then, impurities, such as dopant gas 16, which can be diborane (B2H6), is introduced into the side wall of the trench 15 via vapor phase diffusion to form an isolation layer 17 of a p-type diffused layer (FIG. 12C). In this case, after the trench 15 is filled back with a reinforcing material of an epitaxial silicon film or a polysilicon film, dicing is carried out along a scribing line, by which an IGBT chip is cut from the semiconductor wafer 14.
Such a method of providing the trench 15 and forming the isolation layer 17 on the side wall of the trench 15 is disclosed in JP-A-2-22869, JP-A-2001-185727, and JP-A-2002-76017. JP-A-2-22869 discloses forming a trench from the top surface of a device to a bottom side junction so as to surround an active layer, and then forming a diffusion layer on the side wall of the trench to form an isolation layer with an end of the bottom side junction of the device made extending to the top surface of the device. JP-A-2001-185727 and JP-A-2002-76017 disclose, like JP-A-2-22869, forming a trench from the top surface of the device to a bottom junction and then forming a diffused layer on the side wall of the trench to thereby form a device having a reverse-blocking capability.
In the method of forming the isolation layer in the reverse-blocking IGBT shown in FIGS. 10 and 11, a long time diffusion treatment in a high temperature environment is necessary for diffusing boron from the boron source 4 (a liquid diffusion source of boron) to coat on the surface to form the isolation layer 5 with a diffusion depth of the order of several hundreds micrometers. This, however, can fatigue quartz fixtures, forming a diffusion furnace, such as a quartz board, a quartz tube, and a quartz nozzle, and contaminate by foreign materials from a heater and strength reduction due to devitrification of the quartz fixtures.
Moreover, in forming the isolation layer 5 by the coating and diffusion method, it becomes necessary to form a masking oxide film (the oxide film 2). The masking oxide film needs to be thick and high quality to withstand long time boron diffusion. A silicon oxide film with high resistance of mask, that is, with a high quality, can be formed by a thermal oxidation method. However, in order that no boron atoms penetrate through the masking oxide film in the high temperature and long time (at 1300° C. for 200 hours, for example) diffusion processing of the isolation layer 5 with boron, it is necessary to form a thermal oxide film with a film thickness of about 2.5 μm. For forming such a thermal oxide film with the film thickness of about 2.5 μm, an oxidation time required at an oxidation temperature of 1150° C., for example, is about 200 hours in the dry atmosphere of oxygen by which a high quality oxide film can be obtained.
Even with wet or pyrogenic oxidation, which is known to shorten oxidation time in comparison with the dry oxidation, albeit with slight inferiority in quality of an obtained oxidized film, a long oxidation time of about 15 hours is still necessary. Furthermore, in the above oxidation processing, a large amount of oxygen is introduced into a silicon wafer. This introduces crystal defects, such as oxygen precipitates and oxidation-induced stacking faults (OSF), and produces oxygen donors to thereby cause adverse effects, such as characteristics deterioration and reliability degradation of the device.
Furthermore, also in the step of diffusing boron carried out after the boron source 4 has been coated, the above high temperature and long time diffusion processing is usually carried out under an oxidizing atmosphere. This causes oxygen atoms to be introduced into crystal lattices in the wafer as interstitial oxygen atoms. Thus, also in the diffusion step, crystal defects, such as oxygen precipitates, oxygen donor production, OSF, and slip dislocations are introduced. It is known that a leak current is increased in a p-n junction formed in a wafer with such crystal defects and a breakdown voltage and reliability are significantly degraded in an insulator film formed on the wafer by thermal oxidation. Moreover, oxygen atoms taken in during diffusion processing are made to become donors by another heat treatment to cause an adverse effect of lowering the breakdown voltage.
In the method of forming the isolation layer shown in FIGS. 10 and 11, approximately isotropic diffusion of boron progresses toward a silicon bulk from the opening of the masking oxide film. Thus, the boron diffusion up to 200 μm in the depth direction causes the boron to be inevitably diffused also in the lateral direction on the order of 180 μm. This causes an adverse effect on reduction in a device pitch and a chip size.
In the manufacturing method shown in FIGS. 12A-12C, the trench 15 is formed by dry etching and boron is introduced into the side wall of the formed trench 15 to form the isolation layer 17. Thereafter, the trench 15 is filled with the reinforcing material such as an insulator film or a semiconductor film. Since a trench with a high aspect ratio can be formed, the forming method shown in FIGS. 12A-12C is more advantageous for reducing a device pitch as compared with the forming method shown in FIG. 10. However, the processing time required for etching to a depth of the order of 200 μm is on the order of as long as 100 minutes per one wafer when a typical dry etching device is used. This brings adverse effects such as an increase in a lead time and the number of maintenance. Moreover, when a deep trench is formed by dry etching with a silicon oxide (SiO2) film used as a mask, a thick silicon oxide film with a thickness of several micrometers is necessary because the etching selectivity is on the order of 50. The thick silicon oxide film causes adverse effects such as increase in a cost and reduction in a rate of acceptable products due to introduction of process induced crystal defects, such as OSFs and oxygen precipitates.
Further, in the process of forming an isolation layer in which a deep trench with a high aspect ratio formed by dry etching, there is a problem in that residues, such as a chemical residue 18 and a photo-resist residue 19 are left in the trench as shown in FIG. 12D to cause adverse effects, such as reduction in yield and reduction in reliability. When a dopant such as phosphorus or boron is introduced into the side wall of a trench, the vertically provided side wall of the trench causes the dopant introduction to be usually carried out by implanting dopant ions with the wafer inclined.
Introduction of a dopant into the side wall of the trench having a high aspect ratio is carried out by ion implantation incident at a slight angle of inclination (ion implantation from the top surface of a wafer onto a side wall of a trench having a large angle of inclination to the bottom surface of the wafer). This causes, as shown in FIGS. 13A and 13B, and 14, each being a schematic diagram for explaining problems in ion implantation incident at a slight angle of inclination, adverse effects, such as reduction in an effective dose (and an accompanied increase in an implantation time), a decrease in an effective projected range, a dose loss due to presence of a screen oxide film 14, and reduction in implantation uniformity. Moreover, in a side wall 15 of a trench, a dose and a depth of implanted dopant ions 13 are reduced compared with those to the top surface of the wafer as a principal surface. Furthermore, implanted dopant ions 13 are sometimes absorbed in the screen oxide film 14, reflected, and re-emitted to cause a dose loss. In addition, as shown in FIG. 6A as a characteristic diagram showing a relationship between a angle of inclination and a relative ion implantation time, for a trench formed by ordinary dry etching to have a side wall with a large angle of inclination of 80° or more to the bottom surface, a very long implantation time is required when an ion beam is made incident vertically to a wafer. Therefore, as a measure taken for effectively introducing an impurity into a trench having a high aspect ratio, vapor phase diffusion is used instead of implanting dopant ions into a wafer. In the vapor phase diffusion, a wafer is exposed to a gasified atmosphere of a dopant, such as PH3 (phosphine) or B2H6 (diborane). The vapor phase diffusion, however, is inferior in fine controllability of dose as compared with ion implantation. Moreover, doses of dopant ions that can be introduced are often limited by their solubility limits.
Moreover, when a trench having a high aspect ratio is filled with an insulator film, a space referred to as a void is produced in the trench to cause a problem, such as reduction in reliability. When a deep trench is formed by dry etching, the surface of a wafer is exposed to a plasma atmosphere for a long time. This causes a plasma damage of the wafer, which degrades the device characteristics. In particular, a gate structure in an IGBT is susceptible to plasma damage. Therefore, the trench formation by dry etching is limited to a formation step carried out before a gate structure formation step. Furthermore, even after the gate structure has been formed, there still remains many semiconductor manufacturing process steps that must be undergone, such as a formation step of an emitter structure and a formation step of a passivation layer. When such processing steps are carried out with the formed trench left exposed, residues of resists and chemicals collected therein can cause the product to malfunction. Hence, the trench must be filled with a semiconductor film or an insulator film, which increases the manufacturing cost. Furthermore, when a trench formed by dry etching with a high aspect ratio is filled with an insulator film or a semiconductor film, a space referred to as a void is produced in the trench to sometimes cause a reliability problem.
Moreover, in forming an isolation layer by coating and diffusion, a section where the collector diffused layer and the diffused layer of the isolation layer connect with each other forms a sharp angle at the edge of the bottom of the chip. This can degrade the breakdown voltage due to electric field concentration. Furthermore, when a V-shaped trench is formed by etching, carried out from a first principal surface (top surface) side on which a MOS gate structure is formed, a device pitch is increased. In addition, the section where the collector diffused layer and the diffused layer of the isolation layer connect with each other forms a sharp angle at the edge of the bottom of the chip. This can also degrade the breakdown voltage due to electric field concentration. Moreover, a vertically formed trench tends to cause a laser beam to be incident parallel to a trench side wall to make it more difficult to activate the dopant impurities at the side wall.
Accordingly, there still remains a need for improving the manufacturing process for a semiconductor device, where dopant ions implanted into a side wall of a trench can be more readily activated. There still remains a need for a semiconductor device having high reliability, a small device pitch and a small chip size. Moreover, there still remains a need for improving the manufacturing a semiconductor device, where an isolation layer can be formed without carrying out high temperature and long time diffusion processing and long time oxidation processing. The present invention addresses these needs.